RISC-V support

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RISC-V support

Michael Matz-4
Hi,

On Fri, 21 Jun 2019, Larry Doolittle wrote:

>> Every compiler has its own benefits. That's why tcc still exists
>> in particular. :)
>
> Right.  Wake me when clang can target MSP430 and microblaze.
>
> Adding RISC-V support to tcc would be _extremely_ interesting.

Pushed to mob.  Tested on openSUSE and Debian riscv64 distros, but only
via a qemu, not on real hardware.  The thing is enough to compile itself
and the full testsuite, so it's reasonably complete (e.g. the fancy
argument passing and long double support is there).  No compressed code is
generated, inline asm isn't supported.  Given the limitations of the TCC
code generator the quality of the generated code is on par with the other
architectures (i.e. horrible :-) ).

I did my best to test the other targets, but only checked armhf, aarch64,
i386 and x86-64 on linux; i.e. the windows backends weren't checked.

Still, have fun.


Ciao,
Michael.

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Re: RISC-V support

Christian Jullien-3
Michael,

First of all, I would like to send you huge thanks for your investments in tcc project.
RISC-V backend is, IMHO a very valuable addition to tcc even if the number of real hardware is currently low.
I'm very impatient to have access to real board now.

I'll try to contact the few RISC-V vendors to ask them to add one of their machines to the gnufarm.

The very least thing I can do is to test tcc on machines you don't have access to and I'm very glad to tell you that my Windows 32/64 backends tcc reproducible builds still work ROOTB.

As usual, you did a very good job.

May I suggest you to add a copyright/license header for the new files you added + section on RELICENSING?

Question, what RISC-V flavor(s) do you support, i.e. what is the minimal RSIC-V subset do you require? If I've read correctly, RISC-V is a modular architecture with optional features (hard float, MMU..)

C.

-----Original Message-----
From: Tinycc-devel [mailto:tinycc-devel-bounces+eligis=[hidden email]] On Behalf Of Michael Matz
Sent: Monday, September 02, 2019 00:42
To: [hidden email]
Subject: [Tinycc-devel] RISC-V support

Hi,

On Fri, 21 Jun 2019, Larry Doolittle wrote:

>> Every compiler has its own benefits. That's why tcc still exists
>> in particular. :)
>
> Right.  Wake me when clang can target MSP430 and microblaze.
>
> Adding RISC-V support to tcc would be _extremely_ interesting.

Pushed to mob.  Tested on openSUSE and Debian riscv64 distros, but only
via a qemu, not on real hardware.  The thing is enough to compile itself
and the full testsuite, so it's reasonably complete (e.g. the fancy
argument passing and long double support is there).  No compressed code is
generated, inline asm isn't supported.  Given the limitations of the TCC
code generator the quality of the generated code is on par with the other
architectures (i.e. horrible :-) ).

I did my best to test the other targets, but only checked armhf, aarch64,
i386 and x86-64 on linux; i.e. the windows backends weren't checked.

Still, have fun.


Ciao,
Michael.

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Re: RISC-V support

Giovanni Mascellani
In reply to this post by Michael Matz-4
Il 02/09/19 00:42, Michael Matz ha scritto:
> Pushed to mob.  Tested on openSUSE and Debian riscv64 distros, but only
> via a qemu, not on real hardware.

This is wonderful news, thank you very much!

Giovanni.
--
Giovanni Mascellani <[hidden email]>
Postdoc researcher - Université Libre de Bruxelles


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Re: RISC-V support

Michael Matz-4
In reply to this post by Christian Jullien-3
Hello,

On Mon, 2 Sep 2019, Christian Jullien wrote:

> Question, what RISC-V flavor(s) do you support, i.e. what is the minimal
> RSIC-V subset do you require? If I've read correctly, RISC-V is a
> modular architecture with optional features (hard float, MMU..)

So, it's using the RV64IMFD subsets.  When the sources don't contain float
or double arithmetic the FD subsets aren't used, but I do rely on the
existence of M for any multiplications and divisions (by non-power-of-2).


Ciao,
Michael.


>
> C.
>
> -----Original Message-----
> From: Tinycc-devel [mailto:tinycc-devel-bounces+eligis=[hidden email]] On Behalf Of Michael Matz
> Sent: Monday, September 02, 2019 00:42
> To: [hidden email]
> Subject: [Tinycc-devel] RISC-V support
>
> Hi,
>
> On Fri, 21 Jun 2019, Larry Doolittle wrote:
>
> >> Every compiler has its own benefits. That's why tcc still exists
> >> in particular. :)
> >
> > Right.  Wake me when clang can target MSP430 and microblaze.
> >
> > Adding RISC-V support to tcc would be _extremely_ interesting.
>
> Pushed to mob.  Tested on openSUSE and Debian riscv64 distros, but only
> via a qemu, not on real hardware.  The thing is enough to compile itself
> and the full testsuite, so it's reasonably complete (e.g. the fancy
> argument passing and long double support is there).  No compressed code is
> generated, inline asm isn't supported.  Given the limitations of the TCC
> code generator the quality of the generated code is on par with the other
> architectures (i.e. horrible :-) ).
>
> I did my best to test the other targets, but only checked armhf, aarch64,
> i386 and x86-64 on linux; i.e. the windows backends weren't checked.
>
> Still, have fun.
>
>
> Ciao,
> Michael.
>
> _______________________________________________
> Tinycc-devel mailing list
> [hidden email]
> https://lists.nongnu.org/mailman/listinfo/tinycc-devel
>
>
> _______________________________________________
> Tinycc-devel mailing list
> [hidden email]
> https://lists.nongnu.org/mailman/listinfo/tinycc-devel
>

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Re: RISC-V support

Christian Jullien-3
Ok, that fine.
Does it means that B (https://en.wikipedia.org/wiki/RISC-V#Bit_manipulation)
is currently implemented by soft. IMHO, for system programming it is a must
have. For example, my OpenLisp implementation heavily relies on shift, bit
mask...
Is it something you plan to support? Possibly with specific flags, as gcc
does like: -march=rv64ifd

C.
-----Original Message-----
From: Michael Matz [mailto:[hidden email]]
Sent: Monday, September 02, 2019 21:53
To: [hidden email]; [hidden email]
Subject: Re: [Tinycc-devel] RISC-V support

Hello,

On Mon, 2 Sep 2019, Christian Jullien wrote:

> Question, what RISC-V flavor(s) do you support, i.e. what is the minimal
> RSIC-V subset do you require? If I've read correctly, RISC-V is a
> modular architecture with optional features (hard float, MMU..)

So, it's using the RV64IMFD subsets.  When the sources don't contain float
or double arithmetic the FD subsets aren't used, but I do rely on the
existence of M for any multiplications and divisions (by non-power-of-2).


Ciao,
Michael.


>
> C.
>
> -----Original Message-----
> From: Tinycc-devel
[mailto:tinycc-devel-bounces+eligis=[hidden email]] On Behalf Of
Michael Matz

> Sent: Monday, September 02, 2019 00:42
> To: [hidden email]
> Subject: [Tinycc-devel] RISC-V support
>
> Hi,
>
> On Fri, 21 Jun 2019, Larry Doolittle wrote:
>
> >> Every compiler has its own benefits. That's why tcc still exists
> >> in particular. :)
> >
> > Right.  Wake me when clang can target MSP430 and microblaze.
> >
> > Adding RISC-V support to tcc would be _extremely_ interesting.
>
> Pushed to mob.  Tested on openSUSE and Debian riscv64 distros, but only
> via a qemu, not on real hardware.  The thing is enough to compile itself
> and the full testsuite, so it's reasonably complete (e.g. the fancy
> argument passing and long double support is there).  No compressed code is

> generated, inline asm isn't supported.  Given the limitations of the TCC
> code generator the quality of the generated code is on par with the other
> architectures (i.e. horrible :-) ).
>
> I did my best to test the other targets, but only checked armhf, aarch64,
> i386 and x86-64 on linux; i.e. the windows backends weren't checked.
>
> Still, have fun.
>
>
> Ciao,
> Michael.
>
> _______________________________________________
> Tinycc-devel mailing list
> [hidden email]
> https://lists.nongnu.org/mailman/listinfo/tinycc-devel
>
>
> _______________________________________________
> Tinycc-devel mailing list
> [hidden email]
> https://lists.nongnu.org/mailman/listinfo/tinycc-devel
>


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Re: RISC-V support

Giovanni Mascellani
Hi,

Il 03/09/19 07:29, Christian Jullien ha scritto:
> Ok, that fine.
> Does it means that B (https://en.wikipedia.org/wiki/RISC-V#Bit_manipulation)
> is currently implemented by soft. IMHO, for system programming it is a must
> have. For example, my OpenLisp implementation heavily relies on shift, bit
> mask...

I have no idea about how Micahel's implementation goes, but are there C
operations that directly map to something in the B extension? Shifts are
in the I "extension", and it is the only bit operation that C directly
supports. An optimizing compiler can recognize (or support by builtins)
more complicated patterns like counting leading zeros or rotating bits,
but it doesn't seems to be tinycc's case, does it? Am I missing something?

Thanks, Giovanni.
--
Giovanni Mascellani <[hidden email]>
Postdoc researcher - Université Libre de Bruxelles


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Re: RISC-V support

Christian Jullien-3
Many thanks for your explanation. If it's the case, I suffices.

C.

-----Original Message-----
From: Tinycc-devel [mailto:tinycc-devel-bounces+eligis=[hidden email]] On Behalf Of Giovanni Mascellani
Sent: Tuesday, September 03, 2019 09:50
To: [hidden email]
Subject: Re: [Tinycc-devel] RISC-V support

Hi,

Il 03/09/19 07:29, Christian Jullien ha scritto:
> Ok, that fine.
> Does it means that B
> (https://en.wikipedia.org/wiki/RISC-V#Bit_manipulation)
> is currently implemented by soft. IMHO, for system programming it is a
> must have. For example, my OpenLisp implementation heavily relies on
> shift, bit mask...

I have no idea about how Micahel's implementation goes, but are there C operations that directly map to something in the B extension? Shifts are in the I "extension", and it is the only bit operation that C directly supports. An optimizing compiler can recognize (or support by builtins) more complicated patterns like counting leading zeros or rotating bits, but it doesn't seems to be tinycc's case, does it? Am I missing something?

Thanks, Giovanni.
--
Giovanni Mascellani <[hidden email]> Postdoc researcher - Université Libre de Bruxelles



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Re: RISC-V support

Charles Lohr
I echo Christian Jullien's request for adding to the RELICENSING file.  It's of value to me that it would work out to be clearly MIT licensed.

On Tue, Sep 3, 2019 at 1:06 AM Christian Jullien <[hidden email]> wrote:
Many thanks for your explanation. If it's the case, I suffices.

C.

-----Original Message-----
From: Tinycc-devel [mailto:[hidden email]=[hidden email]] On Behalf Of Giovanni Mascellani
Sent: Tuesday, September 03, 2019 09:50
To: [hidden email]
Subject: Re: [Tinycc-devel] RISC-V support

Hi,

Il 03/09/19 07:29, Christian Jullien ha scritto:
> Ok, that fine.
> Does it means that B
> (https://en.wikipedia.org/wiki/RISC-V#Bit_manipulation)
> is currently implemented by soft. IMHO, for system programming it is a
> must have. For example, my OpenLisp implementation heavily relies on
> shift, bit mask...

I have no idea about how Micahel's implementation goes, but are there C operations that directly map to something in the B extension? Shifts are in the I "extension", and it is the only bit operation that C directly supports. An optimizing compiler can recognize (or support by builtins) more complicated patterns like counting leading zeros or rotating bits, but it doesn't seems to be tinycc's case, does it? Am I missing something?

Thanks, Giovanni.
--
Giovanni Mascellani <[hidden email]> Postdoc researcher - Université Libre de Bruxelles



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Tinycc-devel mailing list
[hidden email]
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